Systems and methods for calibrating impedance of a low power voltage-mode transmitter driver

ABSTRACT

Systems for calibrating impedances caused by a first component and a second component of a voltage-mode transmitter driver are described herein. The first component includes a first transistor and a first resistor connected to the first transistor, wherein the first component is connected to a voltage source and an output end of the voltage-mode transmitter driver, respectively. The second component includes a second transistor and a second resistor connected to the second transistor, wherein the second component is connected to the output end of the voltage-mode transmitter driver, and a third transistor, respectively. A first gate of the third transistor is applied with a first tunable gate voltage, and the first tunable gate voltage is configured to be tuned to calibrate a first impedance between the output end and a ground to match with a second impedance between the voltage source and the output end.

FIELD OF USE

This disclosure relates to configuration of a low power transmitter driver, and specifically, for calibrating impedances of different cells at a low power voltage-mode transmitter driver.

BACKGROUND OF THE INVENTION

Voltage-mode transmitter drivers are often used in used in chip-to-chip connections in devices such as servers and routers. A voltage-mode transmitter driver usually has two cells, an UP-cell having a transistor and a resistor, and a DOWN-cell having a transistor and a resistor. The joint connecting the UP-cell and the DOWN-cell forms the output terminal of the voltage-mode transmitter driver.

High-speed chip-to-chip interconnection standards often require that the DOWN-cell impedance and the UP-cell impedance match a desired reference impedance to decrease the reflection along the interconnection that degrades signal integrity. In other words, the UP-cell impedance between the power supply (V_(S)) and the output terminal, and the DOWN-cell impedance between the output terminal and ground need to be equivalent to a certain reference impedance value. However, transistors in the UP-cell or the DOWN-cell are usually composed of large size n-type transistors. The resistance of a transistor often varies significantly due to different driving voltage levels, and can be rather volatile due to environmental factors such as temperature, humidity, vibration, etc. Thus, the varying resistances of the n-type transistors, especially during different operation modes of the transistors, in the UP-cell and the DOWN-cell can often lead to the mismatch between the UP-cell impedance and the DOWN-cell impedance. Such mismatch often causes excessive noise in the voltage-mode transmitter driver, and an unstable or even erroneous output at the output terminal of the voltage-mode transmitter driver.

SUMMARY

Embodiments described herein provide a device for calibrating impedances caused by a first component and a second component of a voltage-mode transmitter driver. The first component includes a first transistor and a first resistor connected to the first transistor, wherein the first component is connected to a voltage source and an output end of the voltage-mode transmitter driver, respectively. The second component includes a second transistor and a second resistor connected to the second transistor, wherein the second component is connected to the output end of the voltage-mode transmitter driver, and a third transistor, respectively. A first gate of the third transistor is applied with a first tunable gate voltage, and the first tunable gate voltage is configured to be tuned to calibrate a first impedance between the output end and a ground to match with a second impedance between the voltage source and the output end.

In some embodiments, the device further comprises a replica circuit comprises a replica of the first component including a replica of the first transistor and a replica of the first resistor connected to the replica of the first transistor, wherein the replica of the first component is connected to the voltage source and a replica of the output end of the voltage-mode transmitter driver, respectively. The replica circuit comprises a replica of the second component including a replica of the second transistor and a replica of the second resistor connected to the replica of the second transistor, wherein the replica of the second component is connected to the replica of the output end of the voltage-mode transmitter driver, and a replica of the third transistor, respectively, wherein a second gate of the replica of the first transistor and a third gate of the replica of the second transistor are applied with a second tunable gate voltage, and the fourth gate of the replica of the third transistor is applied with the first tunable voltage, and wherein the second tunable gate voltage is configured to be tuned to calibrate a third impedance between the replica of the output end and the ground to match with a fourth impedance between the voltage source and the replica of the output end.

In some embodiments, the device further comprises a third component including a fourth transistor and a third resistor connected to the fourth transistor, wherein the third component is connected to the replica of the output end of the replica of the voltage-mode transmitter driver, and the ground, wherein a fourth gate of the fourth transistor is applied with the first tunable gate voltage configured to calibrate the third impedance between the replica of the output end and the ground to match with a reference impedance.

In some embodiments, the device further comprises a constant current source connected to the third component, the constant current source being configured to feed a constant current into the third component such that a measurement of a first voltage level at the replica of the output end is indicative of the third impedance between the replica of the output end and the ground.

In some embodiments, the device further comprises a multiplexer connected to a first voltage reference source providing a first reference voltage value and a second voltage reference source providing a second reference voltage value, and a calibration logic unit configured to send a selection signal thereby causing the multiplexer to output one of the first reference voltage value and the second reference voltage value.

In some embodiments, the calibration logic unit is configured to cause the multiplexer to output the first reference voltage value when the replica of the first component is detached from the third component, and the device further comprises a comparator connected to the replica of the output end and the voltage reference source, the comparator being configured to compare the first voltage level detected at the replica of the output end with a first reference voltage value from the voltage reference source.

In some embodiments, the calibration logic unit is configured to receive the first output of the comparator indicative of whether the first voltage level at the replica of the output end is substantially similar to the first reference voltage value. In response to determining that the first output of the comparator indicates that the first voltage level at the replica of the output end deviates from the first reference voltage value, the device sends a first signal to a bias generator thereby causing the bias generator to tune the first tunable gate voltage based on a sign of the first output of the comparator until an updated first output of the comparison indicates that an updated first voltage level at the replica of the output end is substantially similar to the first reference voltage value.

In some embodiments, when the replica of the first component is connected to the third component after the updated first voltage level at the replica of the output end is substantially similar to the first reference voltage value, the calibration logic unit is configured to cause the multiplexer to output the first reference voltage value. In such embodiments, the comparator is configured to compare a second voltage level detected at the replica of the output end with the first reference voltage value. The calibration logic unit is further configured to receive a second output of the comparator indicative of whether the second voltage level at the replica of the output end is substantially similar to the first reference voltage value. In response to determining that the second output of the comparator indicates that the second voltage level at the replica of the output end deviates from the first reference voltage value, the device sends a second signal to the bias generator thereby causing the bias generator to tune the second tunable gate voltage based on a sign of the second output of the comparator until an updated second output of the comparator indicates that an updated second voltage level at the replica of the output end is substantially similar to the first reference voltage value.

In some embodiments, in response to determining that the updated second output of the comparator indicates that the updated second voltage level at the replica of the output end is substantially similar to the first reference voltage value, the device applies the tuned second tunable gate voltage as a transistor driver voltage at both a gate of the first transistor and a gate of the second transistor.

In some embodiments, the calibration logic unit is configured to when the replica of the second component is connected to the constant current source, cause the multiplexer to output the second reference voltage value. The comparator is configured to compare a third voltage level at the replica of the output end with the second reference voltage value, and wherein the calibration logic unit is further configured to receive a third output of the comparator indicative of whether the third voltage level at the replica of the output end is substantially similar to the second reference voltage value. In response to determining that the third output of the comparator indicates that the third voltage level at the replica of the output end deviates from the second reference voltage value, send a third signal to the bias generator thereby causing the bias generator to tune the first tunable gate voltage based on a sign of the third output of the comparator until an updated third output of the comparator indicates that an updated third voltage level at the replica of the output end is substantially similar to the second reference voltage value.

BRIEF DESCRIPTION OF DRAWINGS

Further features of the disclosure, its nature and various advantages will become apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

FIG. 1 is a block diagrams illustrating a low power voltage-mode transmitter driver using an additional transistor applied with a tunable gate voltage to calibrate the impedances of the Up-cell and the DOWN-cell, according to some embodiments described herein;

FIG. 2 is a logic flow diagram illustrating a process to operate the circuit shown in FIG. 1 for calibrating impedance of a voltage-mode transmitter, according to one embodiment described herein;

FIG. 3 is a circuit diagram illustrating a voltage-mode transmitter driver slice and a replica slice to calibrate impedances in the voltage-mode transmitter driver, according to some embodiments described herein; and

FIG. 4 illustrates a circuit diagram of a calibration circuit to calibrate impedances of the UP-cell and Down-cell in the replica slice 201 to the desired impedance value, according to some embodiments herein; and

FIGS. 5a-c is a logic flow diagram illustrating a process 500 to operate the circuit shown in FIG. 4 for calibrating the impedances in a replica slice 201, according to one embodiment described herein.

DETAILED DESCRIPTION

In view of the problem of impedance mismatch in a voltage-mode transmitter driver, systems and methods are described herein to independently calibrate respective impedances of the UP-cell and the DOWN-cell in a low power voltage-mode transmitter driver. In some embodiments, low power voltage-mode transmitter drivers are operative to technology systems such as servers and routers. These systems require high-speed low-power area-efficient chip-to-chip interconnections.

FIG. 1 is a circuit diagram 100 illustrating a low power voltage-mode transmitter driver using an additional transistor applied with a tunable gate voltage to calibrate the impedances of the UP-cell and the DOWN-cell, and FIG. 2 is a logic flow diagram illustrating a process to operate the circuit 100 shown in FIG. 1 for calibrating impedance of a voltage-mode transmitter, according to one embodiment described herein. Circuit diagram 100 of FIG. 1 illustrates a low-power voltage-mode driver modelled as having an UP-cell 102 and a DOWN-cell 104. UP-cell 102 and DOWN-cell 104 may be used to provide different bits of a data stream. The UP-cell 102 includes a transistor 106 and a resistor 108 having one terminal connected to the source of the transistor 106. The source of transistor 106 is connected to a voltage source (V_(S)). The other terminal of the resistor 108 is connected to output 118 of the voltage-mode transmitter driver. In traditional transmitter drivers, a value for resistor 108 is chosen to ensure that the output impedance measured at output terminal 118 is matched to a desired impedance. In such embodiments, the UP cell impedance may be measured as R(108)+1/Gmn1(106), where Gmn1(106) is transconductance of device 106. For example, in traditional transmitters, when the desired impedance is 50 Ohm, a suitable electrical resistance value for resistor 108 may be chosen. The gate terminal of the transistor 106 is connected to an output terminal of voltage driver 120. The voltage driver 120 has an input voltage of VIP and a tunable driving voltage V_(DDR). The driving voltage V_(DDR) is tuned, in an implementation, to vary the output voltage from the voltage driver 120 applied to the gate of transistor 106, and thereby modify the resistance of transistor 106, which in turn changes the impedance of the UP-cell 102 between the voltage source V_(S) and the output terminal 118.

The DOWN-cell 104 includes a resistor 112 having one terminal connected to the output 118, and the other terminal connected to the drain of transistor 114. Transistor 114 is driven by a voltage driver 110, which is similar to voltage driver 120, with an input voltage of V_(IN) and the same tunable driving voltage V_(DDR). Similar to the UP-cell, impedance of the DOWN-cell between the output end 118 and the ground can be changed by tuning the tunable driving voltage V_(DDR).

An additional transistor 116 is connected to the source of transistor 114. Specifically, the source terminal of the transistor 114 is connected to the drain terminal of the n-type transistor 116. The source terminal of the n-type transistor 116 is connected to ground.

The gate terminal of n-type transistor 116 is connected to a tunable gate voltage (V_(G)). In addition to V_(DDR), the gate voltage V_(G) can be tuned to change the resistance of transistor 116, which in turn changes the impedance of the DOWN-cell.

In some embodiments, the transistor 116 may be a p-type transistor instead of an n-type transistor as shown in FIG. 1. In such embodiments, other transistors 106 and 114 may also be p-type transistors instead of n-type transistors.

Circuit 100 as shown in FIG. 1 is operated as shown at process 200 in FIG. 2. At 212, the drain and source terminals of the transistor 106 of UP-cell 102 are connected to the voltage source V_(S) and the output end 118 of the voltage-mode transmitter driver, respectively. At 214, the drain and source terminals of transistor 114 of the DOWN-cell 104 are connected to the output 118 of the voltage-mode transmitter driver and to ground via the additional transistor 116, respectively. At 216, tunable gate voltage V_(G) is applied to the gate of the additional transistor 116. At 218, voltage level of gate voltage V_(G) is tuned to render the DOWN-cell impedance between the output end 118 and a ground to match an impedance of UP-cell between the voltage source V_(S) and the output end 118. By tuning V_(G), the output impedance variation between the impedance of UP-cell 102 and the impedance of DOWN-cell 104 can be decreased.

FIG. 3 is a circuit diagram illustrating a voltage-mode transmitter driver slice and a replica slice to calibrate impedances in the voltage-mode transmitter driver, according to some embodiments described herein. In an implementation, a plurality of identical copies (referred to as “slices”) of the transmitter driver 100 of FIG. 1 are connected in parallel as shown in FIG. 3. Each driver slice includes instantiations of UP-cell 102, DOWN-cell 104 and additional transistor 116. The same voltage driver 120 and 110 may be applied to the UP-cells and DOWN-cells in all driver slices.

The respective impedance of UP-cell or DOWN- can be set to match a desired reference value. For example, a desired impedance of the UP-cell 102 of the low power voltage-mode transmitter driver is 50 ohms. Similarly, a desired impedance of the DOWN-cell 104 of the low power voltage-mode transmitter driver is also 50 ohms so as to match the desired UP-cell impedance. To achieve the target impedance of 50 ohms for both the UP-cell 102 and the DOWN-cell 104, for instance when there are 20 driver slices connected in parallel, each driver slice may need to be tuned to a have a respective UP-cell impedance of 1K ohm. The net impedance of 20 driver slices connected in parallel may be measured using the formula:

$Z_{Net} = \frac{Z}{n}$ Where Z is 1 k ohms (of each driver slice) and n is the number of driver slices (20) to yield Z_(Net) of 50 ohms. In some embodiments, to achieve a different target impedance of the voltage-mode transmitter driver 100, each driver slice may be tuned to render a different impedance value for the respective UP-cell or DOWN-cell impedance.

In order to achieve the desired impedance in the UP-cell 102 and the DOWN-cell 104 of the voltage-mode transmitter driver, a replica slice 201 that is similar to the original driver slice is connected to the original parallelly connected driver slices. By tuning the replica slice to the value of 1 k ohm, each driver slice of the 20 driver slices may be tuned to an impedance of 1 k ohm. This will eventually lead to calibration of the impedance of the UP-cell 102 and DOWN-cell 104 of transmitter driver 100 to the desired value of 50 ohm. The replica slice 201 includes a replica UP-cell 202 and a replica DOWN-cell 204. The replica UP-cell 202 includes transistor 206 which is a replica of transistor 106 and resistor 208 which is a replica of resistor 108. The replica DOWN-cell 204 includes transistor 214 which is a replica of transistor 114 and resistor 212 which is a replica of resistor 112, and replica transistor 216 which is a replica of transistor 116. All the replica components are connected in a similar way as the components are connected in driver 100. Driving voltage V_(DDR) is applied to the gate terminals of the transistors 206 and 214.

The tunable voltages V_(G) and V_(DDR) are to be tuned to calibrate impedances of the replica UP-cell 202 and the replica DOWN-cell 204 to a desired value (1K ohm in this case). As the replica slice is connected to the driver slices in parallel via connection 218, when the impedances in the replica slice reaches the desired value, the tuned voltages V_(G) and V_(DDR) in turn calibrate the impedances in each original driver slice to reach the desired value (1K ohm in this case). FIGS. 4-5C further describes aspects of calibrating the replica slice 201.

FIG. 4 illustrates a circuit diagram of a calibration circuit to calibrate respective impedances of the UP-cell and Down-cell in the replica slice 201 to the desired impedance value, according to some embodiments herein. In some embodiments, the respective impedances of UP-cell 202 and of Down Cell 201 are calibrated independently of each other. The independent calibration of impedance of the UP-cell 202 and DOWN-cell 204 happens with independent voltages V_(G) and V_(G1) tuned by bias generator 302 controlled by calibration logic 304. Calibration circuit 400 is setup to tune replica slice 201. The gate terminal of the transistor 206 of replica UP-cell 202 of replica slice 201 is connected to a switch box 318. Switch box 318 has a switch A, that, when closed, connects the gate terminal of replica transistor 206 to V_(DDR) 210. Switch box 318 has another switch B, that when closed, connects the gate terminal of replica transistor 206 to ground. Similarly, the gate terminal of the transistor 214 of replica UP-cell 202 of replica slice 201 is connected to a switch box 316. Switch box 316 has a switch A, that, when closed, connects the gate terminal of transistor 214 to V_(DDR) 210. Switch box 316 has another switch B, that when closed, connects the gate terminal of transistor 214 to ground. Replica transistor 216 is connected to V_(G) 208.

Additionally, V_(DDR) 210 is connected to the source terminal of transistor 320. The drain terminal of transistor 320 is connected to power source V_(S). The gate terminal of transistor 320 is connected to a bias generator 302, which in turn outputs biased output voltages V_(G1) to apply at the gate of transistor 320, and V_(G) 208 to apply at the gate of replica transistor 216. By tuning V_(G1), the bias generator 302 indirectly changes V_(DDR) 210 through transistor 320. The bias generator 302 is controlled by a calibration logic unit 304, which sends signals to the bias generators to tune the output voltages V_(G) and V_(G1) (and V_(DDR) indirectly), such that the replica UP-cell 202 and replica DOWN-cell 204 of the replica slice 201 both render a desired impedance value.

The calibration logic unit 304 receives two inputs: a clock and an output from a comparator 306. In addition to controlling the bias generator 302, the calibration logic unit 304 also controls switch box 318, switch box 316, switch box 314, switch 326, and a select bit of multiplexer 308, as further described below. Comparator 306 compares measured voltage level at output terminal 328 with a reference voltage value retrieved from multiplexer 308.

In order to tune the impedance of the replica UP-cell 202 independently from the impedance of replica DOWN-cell 204, a second DOWN-cell 312 is added in parallel to replica DOWN-cell 204 in the calibration circuit 300. DOWN-cell 312 includes a transistor 322 and a resistor 324. The source terminal of transistor 322 is connected to ground, and the drain terminal of the transistor 322 is connected to resistor 324. The gate terminal of transistor 322 is connected to a switch box 314. Switch box 314 has a switch A, which, when connected applies voltage V_(G) (connected to the bias generator 302) to the transistor 322. Additionally, switch box 314 has another switch 314B, that, when connected, connects the gate terminal of the transistor 322 to ground. Resistor 324 of DOWN-cell 312 is connected to a switch 326, that connects the resistor 324 to a current source 310.

In order to calibrate the impedances of the replica UP-cell 202, replica DOWN-cell 204, and DOWN-cell 312, the voltage level is measured at output terminal 328. The measured voltage level at output terminal 328 is compared to a reference voltage value at comparator 306. Specifically, there are different reference voltage values that may be selected from multiplexer 308 by the calibration logic 304. The calibration logic 304 provides a selection signal to multiplexer 308 to cause the multiplexer 308 to output one of the available reference voltage values, e.g., based on the stage of calibration. Additionally, based on the output value of the comparator 306, the calibration logic unit 304 sends a signal to the bias generator 302 to tune the output voltages V_(G) and V_(G1), or modifies any of the switches 314, 316, 318 and 326. The detailed operation of different components of circuit diagram 400 is further described in relation to FIGS. 5a-c .

In some embodiments, an impedance of the replica UP-cell 202 is calibrated first and a corresponding value for V_(DDR) 210 is fixed. Subsequently, the impedance of replica DOWN-cell 204 may be calibrated by tuning the voltage V_(G) 208. In order to tune the impedance of replica UP-cell 202, DOWN-cell 312 is deployed. The impedance of DOWN-cell 312 is governed by the resistor 324 and transistor 322. In some embodiments, to achieve a desired impedance of 1K ohms in the replica UP-cell 202 and replica DOWN-cell 204 of the replica slice 201, the impedance of the DOWN-cell 312 is to be fixed at 3K ohms. The desired impedance value of 3 k ohm for DOWN-cell 312 is selected based on a desired impedance value for UP-cell 102 and DOWN-cell 104. In some embodiments, if the desired value of impedance for UP-cell 102 and DOWN-cell 104 is different from 50 ohm, the desired value of impedance of DOWN-cell 312 may be different.

FIGS. 5a-c is a logic flow diagram illustrating a process 500 to operate the circuit shown in FIG. 4 for calibrating the impedances in a replica slice 201, according to one embodiment described herein.

In accordance with an example embodiment, DOWN-cell 312 is first calibrated such that the impedance of DOWN-cell 312 is set to a desired value (e.g., 3 k ohm in this case). At the beginning of impedance calibration of DOWN-cell 312, the calibration logic 304 sends control signals to close switch B at 318, switch B at 316, switch 326, and switch A at 314. Simultaneously, the calibration logic 304 sends control signals to open switch A at 318, switch A at 316, and switch B at 314. By controlling the switches in this manner, transistors 206 and 214 effectively are removed from the circuit, and transistor 322 is connected to current source 310. The calibration logic 304 selects REF1 as the reference voltage from the multiplexer 308, for a reference input to the comparator 306. The second input of the comparator 304 is the voltage measured at output terminal 328.

Specifically, at 502, a constant current from a constant current source 310 is fed to the DOWN-cell 312. This may generate a voltage across the DOWN-cell 312 that may be measured at output terminal 328.

At 504, a voltage level at output terminal 328 is measured, the measured voltage level being indicative of the impedance between the output terminal 328 and the ground. As shown in FIG. 4, the measure voltage level at output terminal 328 is fed into a negative terminal of comparator 306.

At 506, an output is provided from multiplexer 308 connected to a first voltage reference source providing a first reference voltage value REF1 and a second voltage reference source providing a second reference voltage value REF2. At 508, calibration logic unit 304 sends a selection signal thereby causing the multiplexer 308 to output one of the first reference voltage value REF1 and the second reference voltage value REF2. For example, in order to calibrate an impedance across DOWN-cell 312, REF1 reference voltage is selected. In some embodiments, the reference voltage values REF1 and REF2 are pre-defined based on the desired impedance of the UP-cell 102 and the DOWN-cell 104.

At 510, comparator 306 compares the first voltage level detected at the output terminal 328 with reference voltage value REF1 from the multiplexer 308. The output of the comparison that indicates whether the voltage level at output terminal 328 is greater or less than, or substantially similar to the reference voltage REF1 is sent to calibration logic unit 304. As used herein, “substantially similar” is used to mean that two entities are almost identical or equivalent with a tolerable difference due to limited measurement precision.

At 512, calibration logic unit 304 governs whether the output of the comparator 306 indicates that the voltage level at the output terminal 328 deviates from the first reference voltage value REF1.

In response to determining that the output of the comparator 306 indicates that the voltage level at the output terminal 328 deviates from REF1, calibration logic unit 304 sends a signal to bias generator 302 thereby causing the bias generator 302 to tune the tunable gate voltage V_(G) based on a sign of the output of the comparator 306, until an updated output of the comparator 306 indicates that an updated voltage level at the output terminal 328 is substantially similar to the reference voltage value REF1.

For example, in some embodiments, a high positive output from the comparator 306 implies that the voltage at output terminal 328 is too low, and the calibration logic unit 304 will instruct the bias generator 302 to decrease the V_(G) voltage so as to increase the voltage measured across DOWN-cell 312. Similarly, calibration logic 304 may instruct the bias generator 302 to increase the V_(G) 208 if the output of the comparator 306 is low. In some embodiments, the output from multiplexer 308 may be connected to the negative terminal of comparator 306 and the output terminal 328 may be connected to the positive terminal of the comparator 306. In such cases, the response of the calibration logic will also be the opposite of the previous embodiment.

Eventually, the modification of V_(G) using bias generator 302 based on the signals from the calibration logic unit 304 may bring the voltage at 328 substantially similar to, or at least within a predetermined tolerable range of the REF1 voltage. In such embodiments, a slight increase or decrease in V_(G) will flip the comparator output from high to low or from low to high. At this time, the calibration of the DOWN-cell 312 to the desired impedance of 3K ohms is complete.

Once the voltage at output terminal 328 measured across DOWN-cell 312 reaches a desired value (REF1), replica slice 201 is connected with DOWN-cell 312 to be calibrated. Calibration of replica UP-cell 202 is performed by connecting DOWN-cell 312 to replica UP-cell 202. The calibration logic 304 achieves this configuration by closing switch A at 318, switch B at 316, and switch A at 314, and opening switch B at 318, switch A at 316, switch 326 and switch B at 314. Calibration logic 304 selects REF1 as the voltage reference from multiplexer 308. The voltage REF1 is fed to the positive input of the comparator 306. Calibration logic 304 instructs the bias generator 302 to lock the value of voltage V_(G) configured from the calibration of the DOWN-cell 312.

At 518, replica UP-cell 202 is connected to the DOWN-cell 312. Based on the switch configuration selected by calibration logic 304 as discussed above, replica DOWN-cell 204, and current source 310 are removed from the calibration circuit 300. Replica UP-cell 202 and DOWN-cell 312 are part of the calibration circuit 300. Once replica UP-cell 202 is connected to DOWN-cell 312, a voltage level is measured at output terminal 328.

At 520, comparator 306 compares the voltage level detected at the output terminal 328 with the first reference voltage value REF1.

At decision block 522, calibration logic 304 determines whether the output of the comparator 306 indicates that the second voltage level at the output terminal 328 deviates from the first reference voltage value REF1. The output of the comparator is provided to calibration logic 304. Based on the results, the calibration logic 304 controls the voltage supplied by the bias generator 302 to the calibration circuit 300 via V_(G1) 208.

At 524, in response to determining that the output of the comparator 306 indicates that the voltage level at the output terminal 328 deviates from the first reference voltage value REF1, calibration logic 304 sends a second signal to the bias generator 302 thereby causing the bias generator 302 to tune the second tunable gate voltage V_(G1) based on a sign of the second output of the comparator 306 until an updated second output of the comparator 306 indicates that an updated second voltage level at the output terminal is substantially similar to the first reference voltage value REF1.

At 526, in response to determining that the output of the comparator 306 indicates that the first voltage level at the output terminal 328 does not deviate from, but is substantially similar to the first reference voltage value REF1, calibration logic 304 applies the tuned second tunable gate voltage V_(G1) as a transistor driver voltage at both a gate of the transistor 106 and a gate of the second transistor 114.

As described during the calibration of DOWN-cell 312 previously, the calibration logic 304 controls the bias generator 302 to tune the voltage V_(G1) to change V_(DDR) based on the results received from comparator 306. During this process, the voltage V_(G) is maintained at the value selected during the time of calibration of DOWN-cell 312. In some embodiments, when the output of comparator 306 is high, means the impedance of the Replica UP-cell 202 is too large, and the calibration logic will instruct the bias generator 302 to increase the V_(G1) voltage in order to increase V_(DDR) 210 and thereby decrease impedance of replica UP-cell 202. On the other hand, calibration logic unit 304 will instruct the bias generator 302 to reduce the voltage V_(G1) in order to reduce voltage V_(DDR) 210 if the output of the comparator is low. The process is repeated until the voltage measured at 328 is within a tolerable range of REF1 voltage.

Once the voltage at output terminal 328 is substantially similar to REF1, it is noted, in accordance with Ohm's law (V=I×R), that the impedance of the replica UP-cell 202 is 1K ohm. The calibration logic 304 switches the configuration of calibration circuit 300 to calibrate the impedance of the replica DOWN-cell 204 to 1K ohm.

Continuing on with 530, DOWN-cell 204 is connected to the constant current source 310 while the calibration logic 304 sends control signals to close switch B at 318, switch A at 316, switch 326, and switch B at 314, and open switch A at 318, switch B at 314 and switch A at 316. The calibration logic 304 selects REF2 at multiplexer 308 as the reference voltage to be fed into the positive input of comparator 306. The reference voltage is swapped from REF1 to REF2, because the desired impedance for Replica DOWN-cell 204 is different from the desired impedance for DOWN-cell 312. According to this configuration of calibration circuit 300, the replica UP-cell 202 and DOWN-cell 312 are removed from the circuit. Replica DOWN-cell 204 is connected to current source 310. The current source 310 will feed a fixed amount of current into replica DOWN-cell 204 to generate a voltage across replica DOWN-cell 204 that may be measured at 328.

At 532, comparator 306 compares the voltage measured at output terminal 328 with the REF2 reference voltage received from multiplexer 308. Calibration logic 304 changes the selection bit value of multiplexer 308 to select REF2 instead of REF1. The output of the comparison is fed to calibration logic 304.

At 534, the calibration logic 304 determines whether the output of the comparator indicates that the voltage level at the output terminal 328 deviates from the second reference voltage value REF2.

At 536, in response to determining that the output of the comparator indicates that the voltage level at the output terminal 328 deviates from the second reference voltage value REF2, calibration logic 304 sends a signal to the bias generator 302 thereby causing the bias generator 302 to tune the first tunable gate voltage V_(G) based on a sign of the output of the comparator until an updated output of the comparator 306 indicates that an updated voltage level at the output terminal 328 is substantially similar to the second reference voltage value REF2. The calibration logic is configured to instruct the bias generator 302 to modify the value of V_(G) until the measured voltage at output terminal 328 is substantially similar to the REF2 voltage, while keeping the value of V_(G1) fixed at the previously determined value. In some embodiments, when the output of the comparator is high, the impedance of the replica DOWN-cell 204 is too low, and the calibration logic 304 will instruct the bias generator 302 to lower the voltage V_(G) voltage in order to increase the impedance of replica DOWN-cell 204. Similarly, the calibration logic 304 will instruct the bias generator 302 to increase the voltage V_(G) if output of the comparator is low. Calibration of the replica slice is finished when the DOWN-cell impedance is tuned to the desire range.

At 538, in response to determining that the output of the comparator indicates that the voltage level at the output terminal 328 does not deviate from the second reference voltage value REF2, the calibration process is complete. After tuning the impedance of DOWN-cell 312, replica of the replica UP-cell 202 and replica of the replica DOWN-cell 204 to desired values, the calibration process is complete. The calibrated V_(DDR) and V_(G) will be applied to the gate voltages of transistors 106, 114, and 116 of voltage-mode transmitter driver 100 respectively.

While operations are depicted in the drawings in a particular order, this is not to be construed as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed to achieve the desirable results.

The subject matter of this specification has been described in terms of particular aspects, but other aspects can be implemented and are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the process depicted in FIGS. 4 and 5 a-c does not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous. Other variations are within the scope of the following claims. 

What is claimed is:
 1. A device for calibrating impedances caused by a first component and a second component of a voltage-mode transmitter driver, the device comprising: the first component including a first transistor and a first resistor connected to the first transistor, wherein the first component is connected to a voltage source and an output end of the voltage-mode transmitter driver, respectively; the second component including a second transistor and a second resistor connected to the second transistor, wherein the second component is connected to the output end of the voltage-mode transmitter driver, and a third transistor, respectively; and wherein a first gate of the third transistor is applied with a first tunable gate voltage, and the first tunable gate voltage is configured to be tuned to calibrate a first impedance between the output end and a ground to match with a second impedance between the voltage source and the output end.
 2. The device of claim 1, further comprising: a replica circuit comprising: a replica of the first component including a replica of the first transistor and a replica of the first resistor connected to the replica of the first transistor, wherein the replica of the first component is connected to the voltage source and a replica of the output end of the voltage-mode transmitter driver, respectively; a replica of the second component including a replica of the second transistor and a replica of the second resistor connected to the replica of the second transistor, wherein the replica of the second component is connected to the replica of the output end of the voltage-mode transmitter driver, and a replica of the third transistor, respectively; wherein a second gate of the replica of the first transistor and a third gate of the replica of the second transistor are applied with a second tunable gate voltage, and the fourth gate of the replica of the third transistor is applied with the first tunable voltage; and wherein the second tunable gate voltage is configured to be tuned to calibrate a third impedance between the replica of the output end and the ground to match with a fourth impedance between the voltage source and the replica of the output end.
 3. The device of claim 2, further comprising: a third component including a fourth transistor and a third resistor connected to the fourth transistor, wherein the third component is connected to the replica of the output end of the replica of the voltage-mode transmitter driver, and the ground; wherein a fourth gate of the fourth transistor is applied with the first tunable gate voltage configured to calibrate the third impedance between the replica of the output end and the ground to match with a reference impedance.
 4. The device of claim 3, further comprising: a constant current source connected to the third component, the constant current source being configured to feed a constant current into the third component such that a measurement of a first voltage level at the replica of the output end is indicative of the third impedance between the replica of the output end and the ground.
 5. The device of claim 4, further comprising: a multiplexer connected to a first voltage reference source providing a first reference voltage value and a second voltage reference source providing a second reference voltage value; a calibration logic unit configured to send a selection signal thereby causing the multiplexer to output one of the first reference voltage value and the second reference voltage value.
 6. The device of claim 5, wherein the calibration logic unit is configured to cause the multiplexer to output the first reference voltage value when the replica of the first component is detached from the third component, and the device further comprises: a comparator connected to the replica of the output end and the voltage reference source, the comparator being configured to compare the first voltage level detected at the replica of the output end with a first reference voltage value from the voltage reference source.
 7. The device of claim 6, wherein the calibration logic unit is configured to: receive the first output of the comparator indicative of whether the first voltage level at the replica of the output end is substantially similar to the first reference voltage value, and in response to determining that the first output of the comparator indicates that the first voltage level at the replica of the output end deviates from the first reference voltage value: send a first signal to a bias generator thereby causing the bias generator to tune the first tunable gate voltage based on a sign of the first output of the comparator until an updated first output of the comparison indicates that an updated first voltage level at the replica of the output end is substantially similar to the first reference voltage value.
 8. The device of claim 7, wherein, when the replica of the first component is connected to the third component after the updated first voltage level at the replica of the output end is substantially similar to the first reference voltage value: the calibration logic unit is configured to cause the multiplexer to output the first reference voltage value; the comparator is configured to compare a second voltage level detected at the replica of the output end with the first reference voltage value; and the calibration logic unit is further configured to: receive a second output of the comparator indicative of whether the second voltage level at the replica of the output end is substantially similar to the first reference voltage value, and in response to determining that the second output of the comparator indicates that the second voltage level at the replica of the output end deviates from the first reference voltage value: send a second signal to the bias generator thereby causing the bias generator to tune the second tunable gate voltage based on a sign of the second output of the comparator until an updated second output of the comparator indicates that an updated second voltage level at the replica of the output end is substantially similar to the first reference voltage value.
 9. The device of claim 8, wherein the calibration logic unit is further configured to: in response to determining that the updated second output of the comparator indicates that the updated second voltage level at the replica of the output end is substantially similar to the first reference voltage value: apply the tuned second tunable gate voltage as a transistor driver voltage at both a gate of the first transistor and a gate of the second transistor.
 10. The device of claim 9, wherein the calibration logic unit is configured to: when the replica of the second component is connected to the constant current source: cause the multiplexer to output the second reference voltage value; wherein the comparator is configured to compare a third voltage level at the replica of the output end with the second reference voltage value; and wherein the calibration logic unit is further configured to: receive a third output of the comparator indicative of whether the third voltage level at the replica of the output end is substantially similar to the second reference voltage value, and in response to determining that the third output of the comparator indicates that the third voltage level at the replica of the output end deviates from the second reference voltage value: send a third signal to the bias generator thereby causing the bias generator to tune the first tunable gate voltage based on a sign of the third output of the comparator until an updated third output of the comparator indicates that an updated third voltage level at the replica of the output end is substantially similar to the second reference voltage value.
 11. A method for calibrating impedances caused by a first component and a second component of a voltage-mode transmitter driver, the method comprising: connecting, the first component including a first transistor and a first resistor connected to the first transistor, to a voltage source and an output end of the voltage-mode transmitter driver, respectively; connecting, the second component including a second transistor and a second resistor connected to the second transistor, to the output end of the voltage-mode transmitter driver and a third transistor, respectively; and applying a first tunable gate voltage to a first gate of the third transistor; and tuning the first tunable gate voltage to calibrate a first impedance between the output end and a ground to match with a second impedance between the voltage source and the output end.
 12. The method of claim 11, further comprising: connecting, a replica of the first component including a replica of the first transistor and a replica of the first resistor connected to the replica of the first transistor, to the voltage source and a replica of the output end of the voltage-mode transmitter driver, respectively; connecting, a replica of the second component including a replica of the second transistor and a replica of the second resistor connected to the replica of the second transistor, to the replica of the output end of the voltage-mode transmitter driver, and a replica of the third transistor, respectively; applying a second tunable gate voltage to a second gate of the replica of the first transistor and a third gate of the replica of the second transistor; applying the first tunable voltage to the fourth gate of the replica of the third transistor; and tuning the second tunable gate voltage to calibrate a third impedance between the replica of the output end and the ground to match with a fourth impedance between the voltage source and the replica of the output end.
 13. The method of claim 12, further comprising: connecting a third component including a fourth transistor and a third resistor connected to the fourth transistor, to the replica of the output end of the replica of the voltage-mode transmitter driver, and the ground, respectively; and applying the first tunable gate voltage to a fourth gate of the fourth transistor to calibrate the third impedance between the replica of the output end and the ground to match with a reference impedance.
 14. The method of claim 13, further comprising: feeding, via a constant current source connected to the third component, a constant current into the third component; and measuring, a first voltage level at the replica of the output end, that is indicative of the third impedance between the replica of the output end and the ground.
 15. The method of claim 14, further comprising: providing an output from a multiplexer connected to a first voltage reference source providing a first reference voltage value and a second voltage reference source providing a second reference voltage value; and sending, via a calibration logic unit, a selection signal thereby causing the multiplexer to output one of the first reference voltage value and the second reference voltage value.
 16. The method of claim 15, further comprising: causing the multiplexer to output the first reference voltage value when the replica of the first component is detached from the third component; and comparing, at a comparator connected to the replica of the output end and the voltage reference source, the first voltage level detected at the replica of the output end with a first reference voltage value from the voltage reference source.
 17. The method of claim 16, further comprising: receiving the first output of the comparator indicative of whether the first voltage level at the replica of the output end is substantially similar to the first reference voltage value, and in response to determining that the first output of the comparator indicates that the first voltage level at the replica of the output end deviates from the first reference voltage value: sending a first signal to a bias generator thereby causing the bias generator to tune the first tunable gate voltage based on a sign of the first output of the comparator until an updated first output of the comparison indicates that an updated first voltage level at the replica of the output end is substantially similar to the first reference voltage value.
 18. The method of claim 17, further comprising: when the replica of the first component is connected to the third component and after the updated first voltage level at the replica of the output end is substantially similar to the first reference voltage value: causing the multiplexer to output the first reference voltage value; comparing a second voltage level detected at the replica of the output end with the first reference voltage value; receiving a second output of the comparator indicative of whether the second voltage level at the replica of the output end is substantially similar to the first reference voltage value; in response to determining that the second output of the comparator indicates that the second voltage level at the replica of the output end deviates from the first reference voltage value: sending a second signal to the bias generator thereby causing the bias generator to tune the second tunable gate voltage based on a sign of the second output of the comparator until an updated second output of the comparator indicates that an updated second voltage level at the replica of the output end is substantially similar to the first reference voltage value.
 19. The method of claim 18, further comprising: in response to determining that the updated second output of the comparator indicates that the updated second voltage level at the replica of the output end is substantially similar to the first reference voltage value: applying the tuned second tunable gate voltage as a transistor driver voltage at both a gate of the first transistor and a gate of the second transistor.
 20. The method of claim 19, further comprising: when the replica of the second component is connected to the constant current source: causing the multiplexer to output the second reference voltage value; comparing a third voltage level at the replica of the output end with the second reference voltage value; receiving a third output of the comparator indicative of whether the third voltage level at the replica of the output end is substantially similar to the second reference voltage value, and in response to determining that the third output of the comparator indicates that the third voltage level at the replica of the output end deviates from the second reference voltage value: sending a third signal to the bias generator thereby causing the bias generator to tune the first tunable gate voltage based on a sign of the third output of the comparator until an updated third output of the comparator indicates that an updated third voltage level at the replica of the output end is substantially similar to the second reference voltage value. 